When executing algorithms it is desirable to have a register file that can be organized to more advantageously support processing of the varying data types and formats that dynamically occur in a programming application. For example, a register file of large width for high precision operations can be required in one part of an application while single and multiple parallel operations on lower precision data can be required in a different part of the same application. This desire is offset by the hardware cost to implement a wider register file or the hardware cost to implement additional read and write ports. The problem is how to achieve a dynamically configurable register file with extended precision at a reduced hardware cost without affecting general capabilities including performance.